1. Field of the Invention
The present invention relates to a semiconductor device, more particularly relates to a semiconductor device having a cladding layer, more preferably a semiconductor device of the silicon-on-insulator (SOI) structure, and to a process for production of the same. More specifically, the present invention relates to a semiconductor device having an SOI structure in which capacitors are arranged at predetermined intervals in an array, for example, to a dynamic random access memory (DRAM) device, and a process for production of the same.
2. Description of the Related Art
DRAM memory cells are provided with capacitors as charge storage elements. The improvement in the degree of integration of DRAM devices has been accompanied by a reduction in the dimensions of the memory cells and a smaller area for formation of the stacked capacitors, thereby reducing the static capacitance required for the storage of data.
As one method for reducing the size of the memory cells and achieving higher densities and simultaneously securing the capacitance for the charge storage, experiments have been made to form a trench in the semiconductor substrate, form an insulating film in the trench, and form a conductive film at the two sides of the insulating film, thereby forming a capacitor (for example, U.S. Pat. No. 4,990,463).
Further, there is known a semiconductor device having an SOI structure in which a silicon monocrystal film is formed on an insulating substrate (for example, U.S. Pat. No. 5,028,558). A semiconductor device having an SOI structure has the advantage that if the integrated circuit is formed on the silicon monocrystal film, the parasitic capacitance of the wiring can be made smaller and the operating speed of the integrated circuit can be increased and, further, has the advantage that it is possible to prevent a latchup phenomenon of CMOS transistors by forming the n-channel MOS transistor and p-channel MOS transistor in a stripe form.
As one method of producing a semiconductor device having an SOI structure, a technique has been proposed for forming the semiconductor device by cladding (sticking) a supporting substrate to a smooth (flat) layer at the side of the semiconductor device where the integrated circuit is formed. Details of this cladding technique will be described later with reference to specific examples.
In this type of SOI type semiconductor device, for example, a DRAM device, when forming a capacitor with a large capacitance, the conductive material serving as the capacitor electrode is made to project out under the insulating layer formed under the silicon monocrystal semiconductor layer, an insulating film is formed on this conductive electrode, and a conductive layer serving as the counter electrode is formed thereon. In other words, in an SOI type DRAM device, in contrast to the above-mentioned trench structure, when forming a capacitor, the capacitor electrode layer, insulating film, and capacitor counter electrode are formed in a projecting manner.
A partial sectional view of a DRAM device is shown in FIG. 1 as an example of a conventional semiconductor having an SOI structure formed by the cladding method.
In the DRAM device shown in FIG. 1, a monocrystal semiconductor layer 2 wherein two diffusion regions of a MOS transistor, that is, the drain region and source region are to be formed, is formed on the top of a silicon dioxide (SiO.sub.2) insulating film layer 4, resulting in an SOI structure.
Underneath the insulating film layer 4, a capacitor electrode conductive layer (storage node) 6 functioning as one of the capacitor electrodes is formed, in a projecting manner. A capacitor insulating film 10 is laid over the capacitor electrode conductive layer 6. A conductive cell plate layer 12 functioning as the other capacitor electrode (counter electrode) is formed burying the recesses between the projections of the conductive layer 6 and covering the insulating film 10. A charge storage capacitor is formed by the capacitor electrode conductive layer 6, the capacitor insulating film 10, and the conductive cell plate layer 12.
The capacitor electrode conductive layer 6 is electrically connected to one of the diffusion regions of the MOS transistor formed in the semiconductor layer 2, for example, the drain region, through a contact hole 8 formed in the insulating film 4. Under the capacitor electrode conductive layer 6 the cell plate layer 12 is stacked through the capacitor insulating film layer 10. Under this cell plate layer 12 a smoothing (flat) film layer 14 is stacked. The smoothing film layer 14 is heat bonded to the supporting substrate 16.
Note that while not illustrated, on the other side of the semiconductor layer 2 facing the insulating layer 4, there are formed a gate insulating layer, gate electrodes which are formed on the gate insulating layer and used as word lines, an interlayer insulating layer, and bit lines perpendicularly intersecting the word lines. The bit lines are connected to the source region formed in the semiconductor layer 2.
By the above structure, a DRAM memory cell is constructed having a MOS transistor functioning as a transfer gate and the above capacitor functioning as a data storage element.
For such a DRAM device having a projecting capacitor to be increased in the capacitance of the capacitor to the value required for a memory device, one may increase the radius of the projected capacitor electrode conductive layer 6 or make the film thicker. The size of the radius, however, is limited from the viewpoint of the degree of integration, so the thickness should be increased. If the thickness of the capacitor electrode conductive layer 6 (the height of the projection) is increased, it is possible to increase the area of the insulating film layer 10, the capacitor electrode conductive layer 6, and the cell plate layer 12 facing the insulating film layer 10 and possible to increase the capacitance of the capacitor.
Along with increasing the thickness of the capacitor electrode conductive layer 6, a large step-difference (strong step difference) 18 is formed corresponding to the thickness (height) of the capacitor electrode conductive layer 6 at the boundary of a cell formation region A, where the array of the capacitor electrode conductive layers 6 is formed and a cell nonformation region B, where memory cells are not formed, and positioned around the cell formation region A. Due to this large step-difference 18, the smoothing of the surface by the smoothing film layer 14 formed on the cell plate layer 12 becomes insufficient.
The surface of the smoothing layer 14 must be formed to be extremely smooth (for example, see U.S. Pat. No. 5,096,854).
When cladding the supporting substrate 16 having a smooth surface to the smoothing film layer 14 having the above curved surface, if an air bubble 20 is present between these surfaces, the smoothing film layer 14 and the supporting substrate 16 will not be sufficiently bonded, and hence the problem will be encountered of a reduction in the bonding strength therebetween.
The above example shows an SOI type DRAM device of the cladding type, but the above problems are not limited to the SOI type semiconductor devices such as the SOI type DRAM device. They are also problems in various other semiconductor devices using cladding.